Inside the VGA Engine

To most programmers, the VGA card is just a place to dump pixels. You write to 0xA0000, and an image appears. But beneath that simple abstraction lies a complex machine composed of five major functional blocks: the CRT Controller, the Graphics Controller, the Attribute Controller, the DAC, and the subject of this article: the Sequencer.

The Sequencer is the conductor of the VGA orchestra. It generates the fundamental timing signals that drive the memory fetch cycles and coordinates the flow of data from Video RAM to the screen.

The Architecture of the Sequencer

The Sequencer is accessed via I/O ports 0x3C4 (Index) and 0x3C5 (Data). It contains only a handful of registers, but they control the most critical aspects of the card’s operation.

Key Registers

1. Reset Register (Index 00h) Before changing critical timing parameters (like the clock mode), you often have to “stop” the sequencer by writing a reset bit here. It’s like clutching the engine before shifting gears.

2. Clocking Mode Register (Index 01h) This controls the master dot clock.

   • 8/9 Dot Mode: Determines if a character cell is 8 or 9 pixels wide (used for text mode).
   • Dot Clock Divide: Can cut the clock in half, essential for low-resolution modes like 320x200 to run on a monitor expecting a higher frequency signal.

3. Map Mask Register (Index 02h) This is the “Write Mask” for the four memory planes. In Planar Modes (like Mode X or EGA), this register determines which planes receive the CPU’s write data.

   • Bit 0: Enable Write to Plane 0 (Blue / Pixel 0)
   • Bit 1: Enable Write to Plane 1 (Green / Pixel 1)
   • … By setting this to 0x0F (1111b), you can write to all four planes simultaneously, achieving the famous “4x fill rate” speedup.

4. Memory Mode Register (Index 04h) The most famous register for demoscene coders.

   • Bit 3 (Chain-4): When set (default in Mode 13h), the lower 2 bits of the address select the plane. When cleared (Mode X), planes are independent.
   • Bit 2 (Odd/Even): Used to interleave data for text modes. Disabling this is step 2 of entering Mode X.

The Plane Mask Trick

The Map Mask Register (Index 02h) was the secret behind high-speed polygon filling.

Imagine you want to clear the screen to black. Standard Way (CPU loop):

for (int i=0; i<64000; i++) video[i] = 0;
// 64,000 writes

Sequencer Way (Planar):

// Enable writing to ALL 4 planes
outp(0x3C4, 0x02); // Select Map Mask
outp(0x3C5, 0x0F); // Enable Planes 0,1,2,3

// Only 1/4th of the writes are now required!
for (int i=0; i<16000; i++) video[i] = 0;
// 16,000 writes. The hardware expands each write to 4 bytes in VRAM.

This 400% performance boost is why almost all fast 3D games (Flight Simulator, Doom predecessors) used planar modes internally.

Timing and the CRT

The Sequencer generates the “Character Clock” (CCLK), which is the heartbeat of the display. It feeds this clock to the CRT Controller (CRTC). The CRTC counts these clocks to decide when to send:

• HSYNC: Horizontal Sync (End of a line, snap back to left).
• VSYNC: Vertical Sync (End of a frame, snap back to top).

By manipulating the Sequencer’s clock dividers and the CRTC’s “Total Character” counters, hackers found they could create “Tweaked Modes.”

• Mode Q (256x256): Popular for scrolling games as 256 is a power of 2 (easy math).
• Mode Y (320x200): But with different memory mapping.
• Text Mode fonts: By messing with the Character Map Select register (Index 03h), you could upload custom fonts, giving text-mode interfaces (like Norton Commander) a graphical feel.

The VRAM Refresh

Dynamic RAM (DRAM) forgets its data if not read periodically. The Sequencer is responsible for generating “Refresh Cycles.” In the early days, if you messed up the Sequencer timings (e.g., stopping the sequencer for too long to change a register), you would see “snow” or data corruption on the screen because the RAM wasn’t being refreshed. Modern cards (and emulators) are forgiving, but on a 1989 VGA card, programming the Sequencer was a dangerous game.

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Technical Modules

• Technical Demo: Matrix - The falling characters effect often utilized custom text-mode fonts uploaded via the Sequencer.
• Technical Demo: Interference - Some interference patterns exploited the timing mismatch between read/write cycles.

Source & Further Reading

• “The Programmer’s Guide to the EGA and VGA Cards” by Richard Ferraro.
• VGA Hardware Register Reference: The FreeVGA project’s map of the Sequencer blocks. External Link
• IBM VGA Technical Reference (1987): Original hardware specifications from IBM.
• “Graphics Programming in C”: A look at register-level optimizations.